99 lines
2.7 KiB
C
99 lines
2.7 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2019-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _UART_H_
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#define _UART_H_
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#include <utils/types.h>
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#define UART_A 0
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#define UART_B 1
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#define UART_C 2
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#define UART_D 3
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#define UART_E 4
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#define BAUD_115200 115200
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#define UART_TX_IDLE 0x1
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#define UART_RX_IDLE 0x2
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#define UART_TX_FIFO_FULL 0x100
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#define UART_RX_FIFO_EMPTY 0x200
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#define UART_INVERT_RXD 0x01
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#define UART_INVERT_TXD 0x02
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#define UART_INVERT_CTS 0x04
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#define UART_INVERT_RTS 0x08
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#define UART_IER_DLAB_IE_EORD 0x20
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#define UART_LCR_DLAB 0x80
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#define UART_LCR_STOP 0x4
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#define UART_LCR_WORD_LENGTH_8 0x3
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#define UART_LSR_RDR 0x1
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#define UART_LSR_THRE 0x20
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#define UART_LSR_TMTY 0x40
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#define UART_LSR_FIFOE 0x80
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#define UART_IIR_FCR_TX_CLR 0x4
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#define UART_IIR_FCR_RX_CLR 0x2
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#define UART_IIR_FCR_EN_FIFO 0x1
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#define UART_IIR_NO_INT BIT(0)
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#define UART_IIR_INT_MASK 0xF
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/* Custom returned interrupt results. Actual interrupts are -1 */
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#define UART_IIR_NOI 0 // No interrupt.
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#define UART_IIR_MSI 1 // Modem status interrupt.
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#define UART_IIR_THRI 2 // Transmitter holding register empty.
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#define UART_IIR_RDI 3 // Receiver data interrupt.
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#define UART_IIR_ERROR 4 // Overrun Error, Parity Error, Framing Error, Break.
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#define UART_IIR_REDI 5 // Receiver end of data interrupt.
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#define UART_IIR_RDTI 7 // Receiver data timeout interrupt.
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#define UART_MCR_RTS 0x2
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#define UART_MCR_DTR 0x1
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typedef struct _uart_t
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{
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/* 0x00 */ vu32 UART_THR_DLAB;
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/* 0x04 */ vu32 UART_IER_DLAB;
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/* 0x08 */ vu32 UART_IIR_FCR;
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/* 0x0C */ vu32 UART_LCR;
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/* 0x10 */ vu32 UART_MCR;
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/* 0x14 */ vu32 UART_LSR;
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/* 0x18 */ vu32 UART_MSR;
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/* 0x1C */ vu32 UART_SPR;
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/* 0x20 */ vu32 UART_IRDA_CSR;
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/* 0x24 */ vu32 UART_RX_FIFO_CFG;
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/* 0x28 */ vu32 UART_MIE;
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/* 0x2C */ vu32 UART_VENDOR_STATUS;
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/* 0x30 */ u8 _pad_30[0xC];
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/* 0x3C */ vu32 UART_ASR;
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} uart_t;
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void uart_init(u32 idx, u32 baud);
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void uart_wait_idle(u32 idx, u32 which);
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void uart_send(u32 idx, const u8 *buf, u32 len);
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u32 uart_recv(u32 idx, u8 *buf, u32 len);
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void uart_invert(u32 idx, bool enable, u32 invert_mask);
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u32 uart_get_IIR(u32 idx);
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void uart_set_IIR(u32 idx);
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void uart_empty_fifo(u32 idx, u32 which);
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#endif
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